ia64_disable_vhpt_walker();
lazy_fp_switch(prev, current);
+ if (prev->arch.dbg_used || next->arch.dbg_used) {
+ /*
+ * Load debug registers either because they are valid or to clear
+ * the previous one.
+ */
+ ia64_load_debug_regs(next->arch.dbr);
+ }
+
prev = ia64_switch_to(next);
/* Note: ia64_switch_to does not return here at vcpu initialization. */
c.nat->privregs_pfn = get_gpfn_from_mfn
(virt_to_maddr(v->arch.privregs) >> PAGE_SHIFT);
+ for (i = 0; i < IA64_NUM_DBG_REGS; i++) {
+ vcpu_get_dbr(v, i, &c.nat->regs.dbr[i]);
+ vcpu_get_ibr(v, i, &c.nat->regs.ibr[i]);
+ }
+
+ for (i = 0; i < 7; i++)
+ vcpu_get_rr(v, (unsigned long)i << 61, &c.nat->regs.rr[i]);
+
/* Fill extra regs. */
for (i = 0; i < 8; i++) {
tr->itrs[i].pte = v->arch.itrs[i].pte.val;
struct domain *d = v->domain;
int was_initialised = v->is_initialised;
unsigned int rbs_size;
- int rc;
+ int rc, i;
/* Finish vcpu initialization. */
if (!was_initialised) {
uregs->ar_rsc |= (2 << 2); /* force PL2/3 */
}
+ for (i = 0; i < IA64_NUM_DBG_REGS; i++) {
+ vcpu_set_dbr(v, i, c.nat->regs.dbr[i]);
+ vcpu_set_ibr(v, i, c.nat->regs.ibr[i]);
+ }
+
if (c.nat->flags & VGCF_EXTRA_REGS) {
- int i;
struct vcpu_tr_regs *tr = &c.nat->regs.tr;
for (i = 0; i < 8; i++) {
IA64FAULT vcpu_set_dbr(VCPU * vcpu, u64 reg, u64 val)
{
- // TODO: unimplemented DBRs return a reserved register fault
- // TODO: Should set Logical CPU state, not just physical
- ia64_set_dbr(reg, val);
+ if (reg >= IA64_NUM_DBG_REGS)
+ return IA64_RSVDREG_FAULT;
+ if ((reg & 1) == 0) {
+ /* Validate address. */
+ if (val >= HYPERVISOR_VIRT_START && val <= HYPERVISOR_VIRT_END)
+ return IA64_ILLOP_FAULT;
+ } else {
+ /* Mask PL0. */
+ val &= ~(1UL << 56);
+ }
+ if (val != 0)
+ vcpu->arch.dbg_used |= (1 << reg);
+ else
+ vcpu->arch.dbg_used &= ~(1 << reg);
+ vcpu->arch.dbr[reg] = val;
+ if (vcpu == current)
+ ia64_set_dbr(reg, val);
return IA64_NO_FAULT;
}
IA64FAULT vcpu_set_ibr(VCPU * vcpu, u64 reg, u64 val)
{
- // TODO: unimplemented IBRs return a reserved register fault
- // TODO: Should set Logical CPU state, not just physical
- ia64_set_ibr(reg, val);
+ if (reg >= IA64_NUM_DBG_REGS)
+ return IA64_RSVDREG_FAULT;
+ if ((reg & 1) == 0) {
+ /* Validate address. */
+ if (val >= HYPERVISOR_VIRT_START && val <= HYPERVISOR_VIRT_END)
+ return IA64_ILLOP_FAULT;
+ } else {
+ /* Mask PL0. */
+ val &= ~(1UL << 56);
+ }
+ if (val != 0)
+ vcpu->arch.dbg_used |= (1 << (reg + IA64_NUM_DBG_REGS));
+ else
+ vcpu->arch.dbg_used &= ~(1 << (reg + IA64_NUM_DBG_REGS));
+ vcpu->arch.ibr[reg] = val;
+ if (vcpu == current)
+ ia64_set_ibr(reg, val);
return IA64_NO_FAULT;
}
IA64FAULT vcpu_get_dbr(VCPU * vcpu, u64 reg, u64 * pval)
{
- // TODO: unimplemented DBRs return a reserved register fault
- u64 val = ia64_get_dbr(reg);
- *pval = val;
+ if (reg >= IA64_NUM_DBG_REGS)
+ return IA64_RSVDREG_FAULT;
+ *pval = vcpu->arch.dbr[reg];
return IA64_NO_FAULT;
}
IA64FAULT vcpu_get_ibr(VCPU * vcpu, u64 reg, u64 * pval)
{
- // TODO: unimplemented IBRs return a reserved register fault
- u64 val = ia64_get_ibr(reg);
- *pval = val;
+ if (reg >= IA64_NUM_DBG_REGS)
+ return IA64_RSVDREG_FAULT;
+ *pval = vcpu->arch.ibr[reg];
return IA64_NO_FAULT;
}
IA64FAULT vcpu_set_rr(VCPU * vcpu, u64 reg, u64 val)
{
PSCB(vcpu, rrs)[reg >> 61] = val;
- // warning: set_one_rr() does it "live"
- set_one_rr(reg, val);
+ if (vcpu == current)
+ set_one_rr(reg, val);
return IA64_NO_FAULT;
}